Anti-Tamper Digital Clocks - An Overview
Anti-Tamper Digital Clocks - An Overview
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In other more in depth aspects of the invention, each with the plurality of delayed monotone signals comprises either a a person or even a zero. The Examine circuit may decide whether the volume of kinds inside the plurality of delayed monotone alerts differs from the h2o level variety by much more than a predetermined threshold.
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twenty five. The strategy for detecting voltage tampering as described in assert 23, whereby using the clock to result in the Assess circuit comprises utilizing a clock edge at an finish in the Appraise time period to trigger the Examine circuit.
an Consider circuit, triggered from the clock, that utilizes the initial plurality of delayed monotone signals or the next plurality of delayed monotone alerts to detect a clock fault.
An aspect of the current invention might reside in a way for detecting voltage tampering. In the tactic, a plurality of resettable delay line segments are supplied. Resettable hold off line segments concerning a resettable hold off line segment connected to a bare minimum delay time and a resettable delay line section associated with a utmost delay time are Each individual connected with discretely increasing hold off situations.
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38. The apparatus for detecting voltage tampering as defined in declare 37, wherein the resettable delay line segments are reset through a reset time period, get more info wherein the reset time period is before the Consider time period.
twelve. The equipment for detecting clock tampering as defined in assert 11, whereby the water level amount is set dependant on delayed monotone alerts from one or more previous clock Consider time.
In additional detailed facets of the creation, the method may well even more include resetting the resettable hold off line segments throughout a reset time period.
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